Single-chip dataprocessors often include a read-only memory (ROM) to store critical interrupt and reset vectors. Often these interrupt and reset vectors are customer specified. In the case of custom dataprocessors and custom microcontroller units (MCUs), customer-supplied programs are also stored in a ROM which is a maskable memory. Mask ROMs are "programmed" at fabrication by using specific masks containing the custom program or customer-specified information. Errors in the manufacture of the masks as well as customer changes to this information are extremely expensive to correct as they require creation of a new mask. Generation of a mask is costly, and therefore it is desirable to avoid errors that occur due to the manufacture of the mask and changes necessitated by code modification.
Other portions of the memory map of a dataprocessor may also be prone to expensive errors. For instance, many single chip dataprocessors include relatively large arrays of electrically erasable programmable ROM (EEPROM) and/or erasable programmable ROM (EPROM). These memories tend to experience a relatively high probability of having one or more defectively manufactured locations. To overcome this situation, accesses to the addresses of defective locations must be mapped to a correct location. There is large circuitry overhead associated with this corrective mapping, as the defective location is not known to the designers of the dataprocessor and therefore circuitry must provide for variable location mapping.
With respect to the single chip dataprocessor, it is necessary to configure the dataprocessor to properly recognize its environment of both on-chip and off-chip peripherals and memory devices. This requires either software monitoring or memory configuration. Software monitoring involves continuously monitoring address outputs and modifying addresses consistent with system configuration. Alternately, the memory map of the dataprocessor may be configured once, presumably at reset, and the resultant mapping is used until the device is powered down or some other predetermined event occurs.
One solution for overcoming defective memory locations and implementing changes to existing non-volatile memories is to use memory patching. Patching a memory involves mapping attempted accesses of a memory location or locations to a replacement location which holds the corrected or non-defective information. The replacement location is called the patch as it contains the information to be used in place of the originally accessed location. The need to patch defective or obsolete ROM by overlaying, or substituting, good memory locations is one which has long been recognized in the context of board-level memory products. Many systems, while applicable to a board-level memory system, are inflexible for application to a dataprocessor.
For example, according to one board-level memory patching scheme, particular locations in an EPROM are substituted for defective or obsolete locations in a ROM by means of a programmable logic array (PLA). The PLA is pre-programmed with information correlating the defective or obsolete addresses with their replacement locations in the EPROM. Again, this example is effective for board-level memory products, but is not particularly suited for implementation in a single chip dataprocessor or MCU.
Other examples perform patching by dedicating control logic to watch for addresses in the desired range of addresses to patch. Typically the desired range will include obsolete code or defective locations. Under these conditions, the dataprocessor actually accesses the patch region when an access is attempted to an address with the desired range. This method is not particularly useful in a single-chip MCU having a variable memory map, nor does it provide flexibility for re-configuration of a system to accommodate changing requirements.
One approach to ROM patching allows for the ability to patch every memory location, thus providing a fine granularity solution. By allowing patching of every memory location, it is possible to correct only those locations which are defective or incorrect. Although a very flexible method of ROM patching, the fine granularity approach requires excess hardware and circuitry in order to effect a patch. Another approach is to patch a block of memory; this method offers patching with coarse granularity and allows for reduced hardware compared to the fine granularity solution. Inefficiency exists when the block of memory to be patched contains good information that does not need to be patched. Therefore, coarse granularity can be redundant and wasteful. Further, the coarse granularity solution requires much memory to store the entire block of correct patch memory. Therefore, a need exists for a fine granularity approach offering flexibility while requiring minimal hardware.